Verifiable compute through precise FP64 matrix multiplication on INT8 tensor cores

I've been delving into a consensus mechanism where the main "work" involves matrix multiplication that's verifiable. I really want to focus on the compute layer here, since it’s based on a result that sounds a bit off: figuring out a precise floating-point product using INT8 math kinda the same vibe ML uses for lossy quantization. The Core Technique (Ozaki Scheme) This technique relies on transformations that are error-free. The goal here is to completely avoid rounding errors: - Break down each floating-point matrix into a sum of bounded integer slices, which can all fit into signed INT8. - Multiply the slice pairs with total precision (INT8 in, INT32 accumulation, zero rounding). - Put together the full product in FP64 by adding the scaled integer results. Nothing gets rounded in this process; the only approximation happens when we prune slice pairs that fall below the target unit in the last place. Math & Performance The crucial point is that the INT32 accumulator is always safe from overflowing. For the operand width b and the inner tile dimension n, each entry of the partial product requires: At b=7, n=512 that’s 14+9=23, which still leaves a lot of space well within INT32 (up to n = 2^17). The cost is pretty straightforward based on the precision target: - FP16: ~2 slices (a few INT8 products) - FP32: ~4 slices (~8-10 products) - FP64: ~8 slices (tens of products) It might sound like a lot until you factor in the speed gain from INT8 a reported Ozaki implementation on INT8 tensor cores has been shown to outperform double-precision cuBLAS by over 4x with zero loss in accuracy. Why this is important for Verifiable Computation Getting a precise and reproducible result is a must for cheap verification. If two machines running the same task end up with the same output, it’s way easier to verify the work done.